A common architecture used in CMOS image sensors is the column parallel analog-to-digital converter (ADC). In image sensors comprising a column parallel ADC, an analog-to-digital conversion element is provided per column of pixels in the imaging array. This architecture has many advantages, such as the low bandwidth requirements of each individual converter element, which implies low noise and low power, and scalability to large array sizes due to the parallel nature of the conversion process.
While designed to be identical, the manufacturing tolerances on each comparator within the ADC mean that each one has a different offset. Thus, for an identical input signal each comparator will latch and store a slightly different digital code. Therefore, the comparator offsets of the column parallel ADC produce a column-wise error in the image. At high gain conditions, when the comparator offset becomes more significant compared to image signal levels, the error comes through as visible vertical lines in the image. This is normally termed vertical fixed pattern noise (VFPN), or fixed pattern noise (FPN), and is extremely annoying to the eye.
A conventional method of removing FPN is to subtract a second dark image data frame from the image data frame. This removes vertical FPN and also pixel level FPN due to pixel offsets and dark current. Although this system is effective in removing FPN, it requires an optical shutter and a frame store, which is an extra cost.